The threat of large scale terrorist attacks has resulted in an increased interest in methods for the detection of weapons of mass destruction and their related materials for homeland security. Of particular interest are passive detection systems (meaning non-intrusive devices detecting the proximity of certain materials), which, if they can be mass produced at low cost and low power, afford the broadest deployment and therefore the most coverage and security. Because radioactive material emits neutrons while self-fissioning, a passive neutron detection device is of particular interest for the detection of clandestine nuclear material.
Recently a semiconductor-based solid state neutron detector has been proposed in which a “neutron conversion layer” (a layer containing a material such as boron isotope 10B which is understood to efficiently react with neutrons to generate high energy charged particles) is placed in very close proximity to an array of charge-sensitize circuits, such as a DRAM memory cell, a FLASH memory cell, or an SRAM memory cell. An industry standard 6-transistor (6T) SRAM cell 100 is illustrated in FIG. 1. For example, U.S. Pat. Nos. 6,867,444 and 7,271,389, assigned to the United States Navy, sets forth two such neutron detection devices and are hereby incorporated by reference herein in their entireties. The 10B doped film reacts with incident neutrons to produce alpha particles that generate charge in the memory cell silicon and cause binary state changes known as single event upsets (SEUs). The upsets, and thus the presence of neutrons, are detected by periodically scanning the memory array and comparing it to the originally loaded data pattern
Though an SRAM, DRAM, or non-volatile memory array may accomplish the above task, it may not be the most ideal candidate for the cell that monitors charged particle induced behavior change. For example, SRAM cells are designed to support random read and write access of individual memory cells (bits) and to store random data patterns. None of this functionality is required for the detection of charge generation and collection; all that is needed is a circuit array that can be periodically scanned for evidence of “hits” by the charged particles generated in the neutron conversion layer.
Further, an SRAM cell is designed for minimum area, and while sufficiently small cells are important, individual circuit cell size is not the real priority. The most important aspect for achieving a low-cost, low-power, mass-producible neutron detection device is the efficiency of the silicon area used. Referring to the case where the neutron conversion layer contains boron isotope 10B and the product of the reaction is alpha particles, the silicon area used by the SRAM cell, for example, is typically very large compared to the cross sectional area that is actually sensitive to a strike by an alpha particle. An area efficiency term can be defined as: the memory cell silicon area in which an alpha particle can induce an upset divided by the total memory cell silicon area. For a charge-sensitive circuit cell ideal for the neutron detector application this ratio would approach 1; in the case of the SRAM cell this ratio may in fact be less than 0.05. And thus 95% of the silicon is wasted, increasing cost, area, and power.
Therefore, it would be desirable to provide an array of semiconductor circuits used in a neutron detection device that makes more efficient use of the silicon area, uses less power, is low cost, and is able to be mass produced.